Powerful data processing systems contain vast hardware resources such as multiple processors and large amounts of storage. An IBM Enterprise Systems Architecture ("ESA")/390 mainframe computer is an example of one such processing system. In order to provide larger amounts of apparent main storage to a user than is available, the main storage of the system is often supplemented with auxiliary storage. As examples, the main system storage is typically semiconductor memory such as random access memory ("RAM"), while the auxiliary storage is often disk storage such as a direct access storage device ("DASD").
With appropriate support by an operating system, main storage and auxiliary storage may be used to provide to a user a system wherein storage appears to be larger than the actual main storage which is available in the configuration. This apparent main storage is referred to as virtual storage, and the addresses used to designate memory locations in the virtual storage are referred to as virtual addresses. The virtual storage of a user may advantageously exceed the size of the actual main storage which is available.
The virtual storage is considered to be composed of blocks of addresses, called pages. Only the most recently referred-to pages of the virtual storage are assigned to occupy blocks of actual main storage. As the user refers to pages of virtual storage that do not appear in main storage, they are brought in to replace pages in main storage that are less likely to be needed. The swapping of pages of storage may be performed by the operating system without the user's knowledge.
One aspect of management of virtual memory is translating virtual addresses to absolute addresses in actual main memory. The conventional technique for translating a virtual address to an absolute address includes a translation from the virtual address to a real address and then a translation from the real address to the absolute address. The following three separately and sequentially performed steps are conventionally required during multiple states of the translation of virtual addresses to absolute addresses:
(1) adding a translation table origin ("tto") value to a translation table index ("tti") value to produce a first adder result; PA1 (2) prefixing and windowing the first adder result of step (1) (this involves multiple comparisons and substitutions of values based upon the comparisons); and PA1 (3) adding an offset to the prefixed and windowed first adder result of step (2) to determine an address of a translation table entry ("atte") that is used in subsequent address translation steps. This offset is referred to later in the text as ZO/MB.
As explained above, one part of the conventional address translation process comprises virtual address to real address translation. This may be conventionally performed by, for example, Dynamic Address Translation ("DAT") and/or Access Register Translation ("ART"), as will be apparent to one of ordinary skill in the art. Specifically, DAT and ART are explained in the IBM ESA/390 Principles of Operation, IBM publication number SA22-7201-02, December 1994, which is hereby incorporated herein by reference in its entirety.
The IBM ESA/390 Principles of Operation document also defines several emulation modes which are relevant to address translation and are set by mode latches. Specifically, separate registers are used in association with different emulation modes. The Start Interpretive Execution ("SIE") instruction initiates an emulation mode. In that regard, the architecture defines a prefix register and a prefixing function which vary based upon the emulation mode. In particular, the host prefix register ("HPFX") applies when no emulation is active, the Guest-1 prefix register ("G1PFX") applies to a first-level SIE guest, and the Guest-2 prefix register ("G2PFX") applies to a second-level SIE guest.
The IBM 370/XA Interpretive Execution Architecture document, IBM publication number SA22-7095-0, January 1984, further defines the Start Interpretive Execution ("SIE") instruction and the operation of a guest program, and is hereby incorporated herein by reference in its entirety. This includes definition of a main storage origin memory begin ("MB") register and main storage limit for the guest. Specifically, the main storage limit is the sum of MB and the extent of the main storage, the sum being contained in a main storage limit ("ML") register for the guest. This architecture also defines the guest versions of the ESA/390 prefix registers discussed hereinabove.
The extension of the ESA/390 Interpretive Execution Architecture to a second level guest is disclosed in U.S. Pat. No. 4,843,541 entitled "Logical Resource Partitioning of a Data Processing System," issued Jun. 27, 1989, and filed Jul. 29, 1987, and hereby incorporated herein by reference in its entirety. Described therein are the zone origin ("ZO") and zone limit ("ZL") registers which operate similarly to the above-discussed MB and ML registers, respectively. Specifically, in an environment using two levels of emulation, the first-level guest uses G1PFX as the prefix register, and operates in the zone of main storage defined by ZO and ZL, while the second-level guest uses G2PFX as the prefix register, and operates in the portion of the first-level guest's zone defined by MB and ML.
By way of further explanation, conventional prefixing is used during the translation of a real address to an absolute address and comprises modifying the first adder result (i.e., the real address produced by step one of the conventional translation routine described above) based upon the results of multiple comparisons. Specifically, if bits 1:19 of the first adder result are zeros, then bits 1:19 are replaced with a selected prefix register (selected from one of HPFX, G1PFX or G2PFX based upon the mode latches). Alternatively, if bits 1:19 of the first adder result are equal to the selected prefix register, then bits 1:19 of the first adder result are replaced by zeroes. Lastly, if bits 1:19 of the first adder result are equal to neither zeroes nor the prefix register, then bits 1:19 remain unchanged. Thus, conventional prefixing is performed.
A Window Address Facility is disclosed in U.S. Pat. No. 5,371,867, entitled "METHOD 0F USING SMALL ADDRESSES TO ACCESS AND GUEST ZONE IN A LARGE MEMORY," issued Dec. 6, 1994 and incorporated herein by reference in its entirety. Described therein are the Window Address Register ("WAR") and the Window Registers WR0 and WR1. The windowing techniques function in conjunction with prefixing such that the absolute address is confined to a width of one memory page.
Conventional windowing comprises modifying the first adder result (step one) based upon the results of multiple comparisons. First, bits 1:18 of the first adder result are compared to the window address register (WAR). If the comparison is negative (unequal), then the first adder result remains unchanged. However, if the comparison is positive (equal), then bits 1:19 of the first adder result are modified. Specifically, if bit 19 of the first adder result is zero (0), then bits 1:19 of the first adder result are replaced by the contents of window register 0 ("WR0"). If bit 19 of the first adder result is one (1), then bits 1:19 of the first adder result are replaced by the window register 1 ("WR1"). Thus, conventional windowing is thereby performed.
The conventional third step completes the determination of the atte. Specifically, an offset value is added to the prefixed and windowed adder result such that the atte table entry is determined.
The above described steps performed within the conventional virtual address to absolute address translation technique has several disadvantages associated with it. First, the adding/prefixing-windowing/offsetting steps within the conventional technique require three complete clock cycles to execute, one for each step. Second, two separate adders are necessary, thus requiring more silicon real estate. Third, three separate control states are present in the conventional design, one state corresponding to each of the three required clock cycles per conversion. This slows the address translation process and makes debugging difficult. Lastly, the multiple stages and adders result in relatively complex circuitry.
The present invention is directed towards solving the above noted problems.